FIG. 1 to FIG. 4 are cross-sectional views illustrating a conventional method of manufacturing a metal-insulator-metal capacitor.
Referring to FIG. 1, a lower metal electrode layer pattern 121 for a MIM capacitor and a lower metal line layer pattern 122 for a metal line are respectively formed on an insulating layer 110 on a semiconductor substrate 100. The metal electrode layer pattern 121 and the lower metal line layer pattern 122 may be formed by performing predetermined patterning after depositing a metal layer. An insulating layer 130 is then formed. A trench 140 exposing the lower metal electrode layer pattern 121 in a MIM capacitor region is formed by an etching process using a predetermined mask layer pattern as an etching mask. Then, a dielectric layer 150 is formed over the entire upper surface of the resultant structure formed with the trench 140. A photoresist layer 160 is formed over the dielectric layer 150 to form an etching mask layer pattern for forming a via hole.
Next, referring to FIG. 2, a photoresist layer pattern 161 is formed exposing the dielectric layer 150 at a region where a via hole is to be formed by exposing and developing the photoresist layer indicated by reference numeral 160 in FIG. 1 using a conventional photolithography method. Then, a via hole 170 exposing the lower metal layer pattern 122 is formed by an etching process using the photoresist layer pattern 161 as an etching mask. After forming the via hole 170, the photoresist layer pattern 161 is removed.
Then, referring to FIG. 3, after removing the photoresist layer pattern 161, a metal layer (not shown) such as a tungsten layer is formed over the entire upper surface of the resultant structure. In addition, a planarization process is performed such that a surface of the dielectric layer 150 is exposed, an upper metal electrode layer 180 is formed within the trench 140 in the MIM capacitor region, and a via contact 190 is formed within the via hole 170 in a metal line region.
Then, referring to FIG. 4, by performing deposition and patterning of a metal layer, upper metal layer patterns 200 and 210 are formed, which are electrically connected to the upper metal electrode layer 180 in the MIM capacitor region and the via contact 190 in the metal line region, respectively.
However, such a conventional method of manufacturing the MIM capacitor may have the following problem. As shown in FIG. 1, in the process of forming the photoresist layer 160, a thickness of the photoresist layer pattern 160 at an upper edge portion A of the trench 140 may be relatively thinner than the thickness of the layer 160 at other portions. In such a case, as explained referring to FIG. 2, a portion of the photoresist layer pattern 161 near the upper edge portion A of the trench 140 may be removed by the etching process for forming the via hole 170, and thereby a groove 141 exposing the lower metal electrode layer pattern 121 may be formed. Then, as shown in FIG. 3, a metal layer 181 may be formed within the groove 141 in the subsequent process of forming a metal layer. The metal layer 181 is not removed by the subsequent planarization process, and, as shown in FIG. 4, it may be connected to the upper metal line layer 200. Consequently, the metal layer 181 may cause an electrical short between the lower metal electrode layer pattern 121 of the MIM capacitor and the upper metal electrode layer 180.